As the density of integrated circuits increases, the dimension between individual devices becomes increasingly small. With this trend, the conventional LOCOS (local oxidation of silicon) method for isolating a device, which forms a field oxide layer via thermal oxidation technique, confronts the limit in the effective isolation length, thereby degrading characteristics of the electrical device isolation. Furthermore, the conventional LOCOS method possesses some inherent drawbacks resulting from the processes, i.e., lateral oxidation of the silicon underneath the silicon nitride mask, making the edge of the field oxide resemble the shape of a bird's beak.
According to the disadvantage for LOCOS isolation structures mentioned above, an isolation technique using shallow trenches has been developed. Generally, the shallow trench isolation (hereinafter referred to as "STI") includes the steps of etching a silicon substrate to form a trench, depositing a CVD (chemical vapor deposition) oxide layer to fill up the trench, and planarizing the CVD oxide layer.
According to the above-mentioned STI technique, the semiconductor substrate is etched at a predetermined depth, thereby providing excellent characteristics of the device isolation. Furthermore, the field oxide layer is formed via a CVD technique, so that the device isolation region that is defined by a photolithography process can be maintained throughout.
However, the STI technique possesses has some drawbacks. Etching the semiconductor substrate produces a damaged layer; an oxidation of the trench produces a stress; and the difference in a coefficient of thermal expansion between the CVD oxide layer and the semiconductor substrate produces a thermal stress during the step of densifying the CVD oxide layer via thermal treatment. Such drawbacks can result in a leakage source, thereby producing more junction current leakages compared with conventional LOCOS techniques.
To overcome the above problems, i.e., to reduce the junction current leakages, a method is proposed wherein the step of densifying the CVD oxide layer is performed at temperature about 1050.degree. C. to 1150.degree. C. so as to cure the damaged layer, thereby reducing the junction current leakages.
FIG. 1 to FIG. 3 are graphs showing the relationship between the current leakage and the distribution respectively in n.sup.+ /p, n.sup.- /p, and p.sup.+ /n junctions measured at a temperature of about 83.degree. C., in accordance with a conventional method.
In FIG. 1 to FIG. 3, the circles 2a, 4a, and 6a show the relationship between the current leakage and the distribution in the case that the densifying of the CVD oxide layer is performed at temperature about 1050.degree. C. and the squares 2b, 4b and 6b show the relationship between the current leakage and the distribution in the case that the densifying of the CVD oxide layer is performed at temperature about 1150.degree. C.
Referring to FIG. 1, in case of an n.sup.+ /p junction, the distribution of the current leakage is illustrated by circles 2a under the densifying temperature about 1050.degree. C., and the distribution of the mean current leakage (50%) is about 4.7.times.10.sup.-14 A/.mu.m. On the other hand, the distribution of the current leakage is illustrated by squares 2b under the densifying temperature about 1150.degree. C., and the distribution of the mean current leakage (50%) is about 3.5.times.10.sup.-14 A/.mu.m.
Referring to FIG. 2, in case of an n.sup.- /p junction, the distribution of the mean current leakage (50%) is about 4.5.times.10.sup.-14 A/.mu.m, as illustrated by circles 4a under the densifying temperature about 1050.degree. C. On the other hand, the mean leakage (50%) is about 3.5.times.10.sup.-14 A/.mu.m, as illustrated by squares 4b under the densifying temperature about 1150.degree. C.
Referring to FIG. 3, in the case of a p.sup.+ /n junction, the distribution of the mean current leakage (50%) is about 3.3.times.10.sup.-14 A/.mu.m, as illustrated by circles 6a under the densifying temperature about 1050.degree. C. On the other hand, the mean leakage (50%) is about 2.7.times.10.sup.-14 A/.mu.m, as illustrated by squares 6b under the densifying temperature about 1150.degree. C.
As illustrated above, we can deduce that as the densifying temperature increases from about 1050.degree. C. to about 1150.degree. C., the junction current leakages reduces in each case.
However, as disclosed in U.S. Pat. No. 5,478,762, "METHOD FOR PRODUCING PATTERNING ALIGNMENT MARKS IN OXIDE", 1995, by Ying-Chen Chao et al., distortions of the semiconductor substrate can occur if the step of densifying the CVD oxide layer is performed at a high temperature of about 1150.degree. C. or more, and the situation can be even worse when the CVD oxide layer is deposited thickly.
Furthermore, if the densifying the CVD oxide layer is performed at temperature of about 1150.degree. C. or more, a step between an active region and inactive region occurs, thereby degrading characteristics of a subsequent gate oxide layer.
Therefore, a method is needed which not only can reduce the current leakage but which can also reduce the distortions of the semiconductor substrate in the art for forming trench isolation.